PREFACE
How This Book Was Written
1.INTRODUCTION
2.MODELING
2.1 Basic concepts
2.2 Functional Modeling at Logic level
2.2.1 Truth Tables and Primitive Cubes
2.2.2 State Tables and Flow Tables
2.2.3 Binary Deision Diagrams
2.2.4 Programs as Functional Models
2.3 functional Modeling at the Register Level
2.3.1 Basic RTL Constructs
2.3.2 Timing Modeling in RTLs
2.3.3 Internal RTL Models
2.4 Structural Models
2.4.1 External Representation
2.4.2 Structural Properties
2.4.3 Internal Representation
2.4.4 Wired Logic and Bibirectionality
2.5 level of Modeling
REFERENCES
PROBLEMS
3.LOGIC SIMULATION
3.1 Applications
3.2 Problems in simulation-Based Design Verification
3.3 Type of simulation
3.4 The Unknown Logic Value
3.5 compiled simulation
3.6 Event-Driven Simulation
3.7 Delay Models
3.7.1 Delay Modeling for Gates
3.7.2 Dealy Modeling for Functional Elements
3.7.3 Delay Modeling in RTLs
3.7.4 Other Aspects of Delay Modeling
3.8 Elemnent Evaluation
3.9 Hazard Detection
3.10 Gate-Level Event-Driven simulation
3.11 Simulation Engines
REFERENCES
PROBLEMS
4. FAULT MODELING
5.FAULT SIMULATION
6.TESTING FOR SINGLE STUCK FAULTS
7.TESTING FOR BRIDGING FAULTS
8.FUNCTIONAL TESTING
9.DESING FOR TESTABILITY
10.COMPRESSION TECHNIQUES
11.BUILT-IN SELF-TEST
12.LOGIC-LEVEL DIAGNOSIS
13.SELF-CHECKING DESIGN
14.PLA TESTING
15.SYSTEM-LEVEL DIAGNOSIS
INDEX